Fabrication of semiconductor features, such as 3D NAND staircase features, requires precise control of multiple steps of photoresist trimming and material etching. In particular, for photoresist trimming, precise control of the trimming time is required to meet targeted dimensions of the photoresist. A lack of process stability and reproducibility results in small chamber condition drift, leading to trim rate variations that are difficult to measure and compensate for. Standard endpoint detection techniques, such as optically measuring the variation of the thickness of etched material within a reactor to determine an endpoint for a material etching process, are ineffective for controlling a photoresist trimming process.
Accordingly, the inventors have provided improved photoresist plasma trimming processes in a semiconductor substrate processing system.